Flash memory devices are a type of EEPROM in which a plurality of memory areas are erased or programmed by one programming operation. Since the EEPROM is capable of being programmed or erased electrically, it is widely used, for example, to store system programming that is continuously updated or as an auxiliary memory device. Particularly, flash EEPROM (hereinafter, referred to as flash memory device) may be used in mass storage devices because its integration may be high as compared to a conventional EEPROM.
Generally, a flash memory system includes a flash memory device and a flash memory controller controlling the flash memory device. The flash memory device comprises a plurality of memory cells arranged in a matrix of rows and columns. The flash memory device may be categorized into NOR-type and NAND-type depending on connection patterns between memory cells and bit lines. The NAND-type flash memory device may be amenable to high integration because it can consume less cell current than the NOR-type flash memory device. The NAND-type flash memory device may be categorized into single level cell (SLC) NAND-type flash memory device and a multi level cell (MLC) NAND-type flash memory device. The SLC NAND-type flash memory is capable of storing one-bit data per cell while the MLC NAND-type flash memory device is capable of storing multi-bit data per cell. MLC NAND-type flash memory devices are disclosed in U.S. Pat Nos. 7,035,144, 6,082,056, and 5,923,586 and U.S. Patent Application Publication No. 2006/0221692, the contents of which are herein incorporated by reference.
In the case that one-bit data is stored to a memory cell during a programming operation, the memory cell has a threshold voltage in either one of two threshold voltage distributions. In other words, the memory cell has a threshold voltage in a threshold voltage distribution corresponding to either one of two states indicating data “1” and data “0”, respectively. In a case where 2-bit data is stored to a memory cell, the memory cell has a threshold voltage in any one of four threshold voltage distributions. In other words, the memory cell has a threshold voltage in a threshold voltage distribution corresponding to one of four states indicating data “11”, data “10”, data “00”, and data “01”, respectively. Further, in the case that three-bit data is stored to a memory cell, the memory cell has a threshold voltage in any one of eight threshold voltage distributions. In a case where four-bit data is stored to a memory cell, the memory cell has a threshold voltage in any one of sixteen threshold voltage distributions, etc.
Threshold voltage distributions corresponding to respective data states exist within a predetermined window. The threshold voltage distributions are controlled precisely so that respective threshold voltage distributions exist within the predetermined window. Generally, flash memory devices are programmed by an incremental step pulse programming (ISPP) scheme which has been utilized to control threshold voltage distributions precisely. An exemplary programming method of the flash memory device using ISPP scheme is disclosed in U.S. Pat. No. 6,266,270 entitled “Non-Volatile Semiconductor Memory and Programming Method of the Same”, the contents of which are herein incorporated by reference.
Threshold voltage distributions corresponding to respective data states should be placed below the highest voltage level of the predetermined window. As the number of data bits stored to respective memory cells is increased, there is also an increase in the number of threshold voltage distributions corresponding to respective data states. In this case, an interval (or margin) between adjacent threshold voltage distributions generally narrows. Threshold voltage distributions corresponding to respective data states may be expanded by various factors. For example, when a programming operation is performed, previously programmed memory cells are affected by coupling with adjacent memory cells that are programmed afterward. This means that threshold voltage distributions may be widened. Thus, in a case where the number of data bits stored to respective memory cells is increased, threshold voltage distributions corresponding to respective data states may be overlapped. In this case, there may be an increase the probability of read error.
The read error may be detected and corrected via an error correction circuit in a flash memory controller. But, if the number of the detected erroneous data bits is increased, the burden of the error correction circuit may be increased more and more.